Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device and method for correcting a write clock and write data.
In a system composed of a plurality of semiconductor elements, a semiconductor device functions to store data. If a data processing device, for example, a memory control unit (MCU) requests data, the semiconductor device outputs the data corresponding to the address inputted from the device which requests the data, or stores the data provided from the device which requests the data, to a position corresponding to the address.
While data is being inputted/outputted between the data processing device and the semiconductor device, if the operating temperature or the operating power of a semiconductor system changes, the phase of the data inputted/outputted between the data processing device and the semiconductor device may vary.
In more detail, it is the norm that the data inputted/outputted between the data processing device and the semiconductor device is inputted/outputted by being synchronized with a clock for transmitting data. In this regard, while the data is being inputted/outputted between the data processing device and the semiconductor device, if the operating temperature or the operating power of a semiconductor system changes, the phase of the data inputted/outputted between the data processing device and the semiconductor device and the phase of the clock for transmitting data are likely to be mismatched so that data having a phase different from that of the initially transmitted data may be inputted/outputted. Due to this fact, a problem can be caused in that the data inputted/outputted between the data processing device and the semiconductor device is likely to be recognized in such a state that it leads or lags by one cycle in comparison with a desired state. That is to say, normal data transmission may be impossible.
For example, describing a procedure of transmitting data from the data processing device to the semiconductor device, the data is transmitted toward the semiconductor device by being synchronized with the center of the clock for transmitting data in the data processing device. In this regard, while transmitting the data, if the operating temperature or the operating power of a semiconductor system changes, the phase of the data may vary so as to be mismatched with the phase of the clock for transmitting data. Due to this fact, the data transmitted from the semiconductor device may not be synchronized with the center of the clock for transmitting data and may fluctuate to some extent so as to either lead or lag. Consequently, a problem can be caused in that the data inputted/outputted between the data processing device and the semiconductor device is likely to be recognized in such a state that it leads or lags by one cycle in comparison with a desired state.
The problem may become more serious as the transmission frequency of the data inputted/outputted between the data processing device and the semiconductor device increases. That is to say, as the transmission frequency of the data inputted/outputted between the data processing device and the semiconductor device increases, the window length of the data to be transmitted becomes very short. Therefore, if a phenomenon, in which the operating temperature or the operating power of a semiconductor system changes, the data inputted/outputted between the data processing device and the semiconductor device is likely to be recognized in such a state that it leads or lags by one cycle in comparison with a desired state.